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hynix semiconductor inc. 8-bit single-chip microcontrollers gms90c320 users manual (ver. 1.2)
version 1.2 published by mcu application team copy right 2001 hynix semiconductor, all right reserved. additional information of this manual may be served by hynix semiconductor offices in korea or distributors and repre- sentatives listed at address directory. hynix semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this manual are correct and reliable; however, hynix semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. revision history version 1.2 (oct. 2000) this book correct the pin number of 44-mqfp package type on page 6. version 1.1 (oct. 1999) before version
gms90c320 oct. 2000 ver 1.2 device naming structure h(g)ms90x320 frequency package type blank: 24mhz blank: pl: q: 40pdip 44plcc 44mqfp enhanced rom-less version operating voltage c: l: normal voltage low voltage hynix semiconductor mcu xxxx mcu series 40: 40mhz 50: 50mhz
gms90c320 oct. 2000 ver 1.2 gms90c320 ordering information operating voltage (v) device name rom size (bytes) ram size (bytes) operating max. frequency (mhz) package type 4.25~5.5 gms90c320 40 gms90c320 pl40 gms90c320 q40 rom-less 256 40 40pdip 44plcc 44mqfp gms90c320 50 gms90c320 pl50 gms90c320 q50 rom-less 256 50 40pdip 44plcc 44mqfp 2.7~5.5 gms90l320 gms90l320 pl gms90l320 q rom-less 256 24 40pdip 44plcc 44mqfp
gms90c320 oct. 2000 ver 1.2 1 gms90c320/l320 cmos single-chip 8-bit microcontroller rom-less version for 90c52 features ? fully compatible to standard mcs-51 microcontroller ? versions for 40/50 mhz operating frequency ? low voltage version for 24mhz operating frequency ? 256 bytes of on-chip data ram ? 64k external program memory space ? 64k external data memory space ? four 8-bit ports ? three 16-bit timers/counters (timer 2 with up/down counter feature) ?usart ? six interrupt sources, two priority levels ? power saving idle and power down mode ? 2.7volt low voltage version available ? p-dip-40, p-lcc-44, p-mqfp-44 package the gms90c320 described in this document is compatible with the standard 80c32 can be used for all present standard 80c32 applications. operating voltage (v) device name rom ram operating frequency (mhz) 4.25~5.5 gms90c320 rom-less 256 8bit 40/50 2.7~5.5 gms90l320 rom-less 256 8bit 24 ram 256 x 8 t0 t1 rom-less cpu 8-bit usart port0 port3 port1 port2 t2 i/o i/o i/o i/o
gms90c320 2 oct. 2000 ver 1.2 44-plcc pin configuration (top view) (p-lcc-44) p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea n.c. ale psen p2.7/a15 p2.6/a14 p2.5/a13 p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 n.c. v cc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 wr /p3.6 rd /p3.7 xtal2 xtal1 v ss n.c. p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p1.5 p1.6 p1.7 reset rxd/p3.0 n.c. txd/p3.1 int0 /p3.2 int1 /p3.3 t0/p3.4 t1/p3.5 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28
gms90c320 oct. 2000 ver 1.2 3 40-pdip pin configuration (top view) (p-dip-40) p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea ale psen p1.6 p1.7 reset rxd/p3.0 txd/p3.1 int0 /p3.2 int1 /p3.3 t0/p3.4 t1/p3.5 wr /p3.6 rd /p3.7 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 t2/p1.0 t2ex/p1.1 p1.2 p1.3 p1.4 p1.5 1 2 3 4 5 6 xtal2 xtal1 v ss 18 19 20 v cc 40 p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 28 27 26 25 24 23 22 21
gms90c320 4 oct. 2000 ver 1.2 44-plcc pin configuration (top view) (p-mqfp-44) p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea n.c. ale psen p2.7/a15 p2.6/a14 p2.5/a13 p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 n.c. v cc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 wr /p3.6 rd /p3.7 xtal2 xtal1 v ss n.c. p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p1.5 p1.6 p1.7 reset rxd/p3.0 n.c. txd/p3.1 int0 /p3.2 int1 /p3.3 t0/p3.4 t1/p3.5 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22
gms90c320 oct. 2000 ver 1.2 5 logic symbol port 0 xtal1 xtal2 reset ea ale psen 8-bit digital i/o port 1 8-bit digital i/o port 2 8-bit digital i/o port 3 8-bit digital i/o v cc v ss
gms90c320 6 oct. 2000 ver 1.2 pin definitions and functions symbol pin number input/ output function p-lcc-44 p-dip-40 p-mqfp- 44 p1.0-p1.7 2-9 1-8 40-44, 1-3 i/o port1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the pulls-ups (i il , in the dc characteristics). pins p1.0 and p1.1 also. port 1 also receives the low-order address byte during program memory verification. port1 also serves alternate functions of timer 2. 2 3 1 2 40 41 p1.0/t2: timer/counter 2 external count input p1.1/t2ex: timer/counter 2 trigger input p3.0-p3.7 11,13- 19 10-17 5, 7- 13 i/o port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. as inputs, port 3 pins being externally pulled low will source current (i il ,in the dc characteristics) because of internal pulls-up resistors. port 3 also serves the special features of the 80c51 family, as listed below. 11 10 5 p3.0/rxd receiver data input (asynchronous) or data input output (synchronous) of the serial interface 0 13 11 7 p3.1 / txd transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 14 12 8 p3.2 / int0 interrupt 0 input /timer0gatecontrol 15 13 9 p3.3 / int1 interrupt 1 input /timer1gatecontrol 16 14 10 p3.4 / t0 counter 0 input 17 15 11 p3.5 / t1 counter 1 input 18 16 12 p3.6 / wr the write control signal latches the data byte from port 0 into the external data memory 19 17 13 p3.7 / rd the read control signal enables the external data memory to port 0 xtal2 20 18 14 o xtal2 output of the inverting oscillator amplifier xtal1 21 19 15 i xtal1 input to the inverting oscillator amplifier and input to the internal clock generator circuits. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left unconnected. there are no require- ments on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide- by-two flip-flop. minimum and maximum high and low times as well as rise fall times specified in the ac characteristics must be observed.
gms90c320 oct. 2000 ver 1.2 7 p2.0-p2.7 24-31 21-28 18-25 i/o port 2 port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the pulls-ups (i il , in the dc characteristics). port 2 emits the high- order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 emits the contents of the p2 special function register. psen 32 29 26 o the program store enable the read strobe to external program memory when the device is executing code from the external program memory. psen is acti- vated twice each machine cycle, except that two psen activation are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. reset 10 9 4 i reset a high level on this pin for two machine cycles while the oscillator is running resets the device. an internal diffused resistor to v ss permits power-on reset using only an external capacitor to v cc . ale 33 30 27 o the address latch enable output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. ea 35 31 29 i external access enable ea must be external held low to enable the device to fetch code from external program memory locations 0000 h to ffff h .ifea is held high, the device executes from internal program memory unless the program counter contains an address greater than its internal memory size. p0.0-p0.7 43-36 39-32 37-30 i/o port 0 port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pull-ups when emitting 1s. port 0 also outputs the code bytes during program verification in the gms97c5x. external pull-up resistors are required during program verification. v ss 22 20 16 - circuit ground potential v cc 44 40 38 - supply terminal for all operating modes n.c. 1,12, 23,34 - 6,17, 28,39 - no connection symbol pin number input/ output function p-lcc-44 p-dip-40 p-mqfp- 44
gms90c320 8 oct. 2000 ver 1.2 function description the gms90 series is fully compatible to the standard 8051 microcontroller family. it is compatible with the standard 80c32. while maintaining all architectural and operational characteristics of the standard 80c32, the gms90c320 incorporates some enhancements in the timer 2 unit. figure 1 shows a block diagram of the gms90c320 figure 1 block diagram of the gms90c320 ram 256 x 8 port 0 port 0 8-bit digital i/o port 1 port 1 8-bit digital i/o port 2 port 2 8-bit digital i/o port 3 port 3 8-bit digital i/o cpu timer 0 timer 1 timer 2 interrupt unit serial channel osc & timing xtal1 xtal2 reset ea ale psen
gms90c320 oct. 2000 ver 1.2 9 cpu the gms90c320 is efficient both as a controller and as an arithmetic processor. it has extensive facilities for binary and bcd arithmetic and excels in its bit-handling capabilities. efficient use of program memory results from an instruction set con- sisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. with a 12 mhz crystal, 58% of the instructions are executed in 1.0 m s. special function register psw reset value of psw is 00 h. bit function cy carry flag ac auxiliary carry flag (for bcd operation) f0 general purpose flag rs1 0 0 1 1 rs0 0 1 0 1 register bank select control bits bank 0 selected, data address 00 h -07 h bank 1 selected, data address 08 h -0f h bank 2 selected, data address 10 h -17 h bank 3 selected, data address 18 h -1f h ov overflow flag f1 general purpose flag p parity flag set/cleared by hardware each instruction cycle to indicate an odd/ even number of one bits in the accumulator, i.e. even parity. msb lsb bitno. 76543210 addr. d0 h cy ac f0 rs1 rs2 ov f1 p psw
gms90c320 10 oct. 2000 ver 1.2 special function registers all registers, except the program counter and the four general purpose register banks, reside in the special function register area. the 27 special function registers (sfr) include pointers and registers that provide an interface between the cpu and the other on-chip peripherals. there are also 128 directly addressable bits within the sfr area. all sfrs are listed in table 1 , table 2 ,and table 3 . in table 1 they are organized in numeric order of their addresses. in table 2 they are organized in groups which refer to the functional blocks of the gms90c320. table 3 illustrates the contents of the sfrs. table 1 special function registers in numeric order of their addresses address register contents after reset address register contents after reset 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h p0 1) sp dpl dph reserved reserved reserved pcon 1) : bit-addressable special function register ff h 07 h 00 h 00 h xx h 2) xx h 2) xx h 2) 0xxx0000 b 2) 2) : x means that the value is indeterminate and the location is reserved a0 h a1 h a2 h a3 h a4 h a5 h a6 h a7 h p2 1) reserved reserved reserved reserved reserved reserved reserved ff h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 88 h 89 h 8a h 8b h 8c h 8d h 8e h 8f h tcon 1) tmod tl0 tl1 th0 th1 reserved reserved 00 h 00 h 00 h 00 h 00 h 00 h xx h 2) xx h 2) a8 h a9 h aa h ab h ac h ad h ae h af h ie 1) reserved reserved reserved reserved reserved reserved reserved 0x000000 b 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h p1 1) reserved reserved reserved reserved reserved reserved reserved ff h 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) b0 h b1 h b2 h b3 h b4 h b5 h b6 h b7 h p3 1) reserved reserved reserved reserved reserved reserved reserved ff h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 98 h 99 h 9a h 9b h 9c h 9d h 9e h 9f h scon 1) sbuf reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) b8 h b9 h ba h bb h bc h bd h be h bf h ip 1) reserved reserved reserved reserved reserved reserved reserved xx000000 b 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2)
gms90c320 oct. 2000 ver 1.2 11 table 1 special function registers in numeric order of their addresses (contd) address register contents after reset address register contents after reset c0 h c1 h c2 h c3 h c4 h c5 h c6 h c7 h reserved reserved reserved reserved reserved reserved reserved reserved xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) e0 h e1 h e2 h e3 h e4 h e5 h e6 h e7 h acc 1) reserved reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) c8 h c9 h ca h cb h cc h cd h ce h cf h t2con 1) t2mod rc2l rc2h tl2 th2 reserved reserved 00 h xxxxxxx0 b 2) 00 h 00 h 00 h 00 h xx h 2) xx h 2) e8 h e9 h ea h eb h ec h ed h ee h ef h reserved reserved reserved reserved reserved reserved reserved reserved xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) d0 h d1 h d2 h d3 h d4 h d5 h d6 h d7 h psw 1) reserved reserved reserved reserved reserved reserved reserved 1) : bit-addressable special function register 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 2) : x means that the value is indeterminate and the location is reserved f0 h f1 h f2 h f3 h f4 h f5 h f6 h f7 h b 1) reserved reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) d8 h d9 h da h db h dc h dd h de h df h reserved reserved reserved reserved reserved reserved reserved reserved xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) f8 h f9 h fa h fb h fc h fd h fe h ff h reserved reserved reserved reserved reserved reserved reserved reserved xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2)
gms90c320 12 oct. 2000 ver 1.2 table 2 special function registers - functional blocks block symbol name address content after reset cpu acc b dph dpl psw sp accumulator b-register data pointer, high byte data pointer, low byte program status word register stack pointer e0 h 1) f0 h 1) 83 h 82 h d0 h 1) 81 h 1) bit-addressable special function registers 00 h 00 h 00 h 00 h 00 h 07 h interrupt system ie ip interrupt enable register interrupt priority register a8 h 1) b8 h 1) 0x000000 b 2) xx000000 b 2) 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks ports p0 p1 p2 p3 port 0 port 1 port 2 port 3 80 h 1) 90 h 1) a0 h 1) b0 h 1) ff h ff h ff h ff h serial channels pcon sbuf scon power control register serial channel buffer register serial channel 0 control register 87 h 99 h 98 h 1) 0xxx0000 b 2) xx h 3) 00 h 3) x means that the value is indetermi nate and the location is reserved timer 0 / timer 1 tcon th0 th1 tl0 tl1 tmod timer 0/1 control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88 h 1) 8c h 8d h 8a h 8b h 89 h 00 h 00 h 00 h 00 h 00 h 00 h timer 2 t2con t2mod rc2h rc2l th2 tl2 timer 2 control register timer 2 mode register timer 2 reload capture register, high byte timer 2 reload capture register, low byte timer 2, high byte timer 2, low byte c8 h 1) c9 h cb h ca h cd h cc h 00 h xxxxxxx0 b 2) 00 h 00 h 00 h 00 h power saving modes pcon power control register 87 h 0xxx0000 b 2)
gms90c320 oct. 2000 ver 1.2 13 table 3 contents of sfrs, sfrs in numeric order address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 h p0 81 h sp 82 h dpl 83 h dph 87 h pcon smod - - - gf1 gf0 pde idle 88 h tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 89 h tmod gate c/t m1 m0 gate c/t m1 m0 8a h tl0 8b h tl1 8c h th0 8d h th1 90 h p1 98 h scon sm0 sm1 sm2 ren tb8 rb8 ti ri 99 h sbuf a0 h p2 a8 h ie ea - et2 es et1 ex1 et0 ex0 b0 h p3 b8 h ip - - pt2 ps pt1 px1 pt0 px0 c8 h t2con tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 c9 h t2mod -------dcen sfr bit and byte addressable sfr not bit addressable - this bit location is reserved.
gms90c320 14 oct. 2000 ver 1.2 table 3 contents of sfrs, sfrs in numeric order (contd) address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ca h rc2l cb h rc2h cc h tl2 cd h th2 d0 h psw cy ac f0 rs1 rs0 ov f1 p e0 h acc f0 h b sfr bit and byte addressable sfr not bit addressable - this bit location is reserved.
gms90c320 oct. 2000 ver 1.2 15 timer/counter0and1 timer/counter 0 and 1 can be used in four operating modes as listed in table 4 : in the timer function (c/t = 0) the register is incremented every machine cycle. therefore the count rate is . in the counter function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (p3.4/t0, p3.5/t1). since it takes two machine cycles to detect a falling edge the max. count rate is . external inputs int0 and int1 (p3.2, p3.3) can be programmed to function as a gate to facilitate pulse width measurements. figure 2 illustrates the input clock logic. figure 2 timer/counter 0 and 1 input clock logic table 4 timer/counter 0 and 1 operating modes mode description tmod input clock gate c/t m1 m0 internal external (max.) 0 8-bit timer/counter with a divide-by-32 prescaler xx0 0 1 16-bit timer/counter xx0 1 2 8-bit timer/counter with 8-bit autoreload xx1 0 3 timer/counter 0 used as one 8-bit timer/counter and one 8- bit timer timer 1 stops xx1 1 | osc 12 32 ------------------- | osc 24 32 ------------------- | osc 12 --------------- - | osc 24 --------------- - | osc 12 --------------- - | osc 24 --------------- - | osc 12 --------------- - | osc 24 --------------- - | osc 12 | osc 24 f osc ? 12 c/t tmod 0 1 gate tmod tr 0/1 tcon p3.4/t0 p3.5/t1 max. f osc /24 p3.2/int0 p3.3/int1 timer 0/1 input clock control | osc 12
gms90c320 16 oct. 2000 ver 1.2 timer 2 timer 2 is a 16-bit timer/counter with an up/down count feature. it can operate either as timer or as an event counter which is selected by bit c/t2 (t2con.1). it has three operating modes as shown in table 5 . 1note: = falling edge table 5 timer/counter 2 operating modes mode t2con t2mo d decn t2con exen p1.1 t2ex remarks input clock rxclk or txclk cp/ rl2 tr2 internal external (p1.0/t2) 16-bit auto- reload 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 x x x 0 1 reload upon overflow reload trigger (falling edge) down counting up counting max. 16-bit capture 0 0 1 1 1 1 x x 0 1 x 16-bit timer/counter (only up-counting) capture th1, tl2 ? rc2h, rc2l max. baud rate generator 1 1 x x 1 1 x x 0 1 x no overflow interrupt request (tf2) extra external interrupt (timer 2) max. off x x 0 x x x timer 2 stops - - | osc 12 --------------- - | osc 24 --------------- - | osc 12 --------------- - | osc 24 --------------- - | osc 12 --------------- - | osc 24 --------------- -
gms90c320 oct. 2000 ver 1.2 17 serial interface (usart) the serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 6 . the possible baud rates can be calculated using the formulas g iven in table 7 . table 6 usart operating modes mode scon baudrate description sm0 sm1 0 0 0 serial data enters and exits through rxd. txd outputs the shift clock. 8-bit are transmitted/received (lsb first) 1 0 1 timer 1/2 overflow rate 8-bit uart 10 bits are transmitted (through txd) or received (rxd) 2 10 or 9-bit uart 11 bits are transmitted (through txd) or received (rxd) 3 1 1 timer 1/2 overflow rate 9-bit uart like mode 2 except the variable baud rate table 7 formulas for calculating baud rates baud rate derived from interface mode baud rate oscillator 0 2 timer 1 (16-bit timer) (8-bit timer with 8-bit autore- load) 1, 3 1, 3 timer 2 1, 3 | osc 12 --------------- - | osc 32 --------------- - | osc 64 --------------- - | osc 12 --------------- - 2 smod | osc 64 ------------------------------------------ 2 smod timer 1 overflow rat e 32 -------------------------------------------------------------------------------- - 2 smod | osc 32 12 256 th1 C () ---------------------------------------------------------- - | osc 32 65536 rc2h,rc2l () C [] ------------------------------------------------------------------------------
gms90c320 18 oct. 2000 ver 1.2 interrupt system the gms90c320 provides 6 interrupt sources with two priority levels. figure 3 gives a general overview of the interrupt sources and illustrates the request and control flags. figure 3 interrupt request sources pt0 ip.1 high priority low priority ea ie.7 tf0 tcon.5 timer 0 overflow tf1 tcon.7 ie0 tcon.1 ie1 tcon.3 tf2 t2con.7 exf2 t2con.6 ri scon.0 ti scon.1 timer 2 overflow timer 1 overflow p3.2/ int0 p3.3/ int1 p1.1/ t2ex usart pt1 ip.3 pt2 ip.5 ps ip.4 px0 ip.0 px1 ip.2 et0 ie.1 et1 ie.3 et2 ie.5 es ie.4 ex0 ie.0 ex1 ie.2 it0 tcon.0 it1 tcon.2 exen2 t2con.3
gms90c320 oct. 2000 ver 1.2 19 a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. a high- priority interrupt cannot be interrupted by any other interrupt source. if two requests of different priority level are received simultaneously, the request of higher priority is serviced. if requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 9 . table 8 interrupt sources and their corresponding interrupt vectors source (request flags) vector vector address ie0 tf0 ie1 tf1 ri+ti tf2+exf2 external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial port interrupt timer 2 interrupt 0003 h 000b h 0013 h 001b h 0023 h 002b h table 9 interrupt priority-within-level interrupt source priority ie0 tf0 ie1 tf1 ri+ti tf2+exf2 external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial port interrupt timer 2 interrupt high low
gms90c320 20 oct. 2000 ver 1.2 power saving modes two power down modes are available, the idle mode and power down mode. the bits pde and idle of the register pcon select the power down mode or the idle mode, respectively. if the power down mode and the idle mode are set at the same time, the power down mode takes precedence. table 10 gives a general overview of the power saving modes. in the power down mode of operation, v cc can be reduced to minimize power consumption. it must be ensured, however, that v cc is not reduced before the power down mode is invoked, and that v cc is restored to its normal operating level, before the power down mode is terminated. the reset signal that terminates the power down mode also restarts the oscillator. the reset should not be activated before v cc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). table 10 power saving modes overview mode entering instruction example leaving by remarks idle mode orl pcon,#01h - enabled interrupt - hardware reset cpu is gated off cpu status registers maintain their data. peripherals are active power-down mode orl pcon,#02h hardware reset oscillator is stopped, contents of on-chip ram and sfrs are main- tained (leaving power down mode means redefinition of sfr con- tents).
gms90c320 oct. 2000 ver 1.2 21 absolute maximum ratings ambient temperature under bias (t a ) .......................................................................................................-40 to + 85 c storage temperature (t st )..........................................................................................................................-65 t o+150 c voltage on v cc pins with respect to ground (v ss ).....................................................................................-0.5 v to 6.5 v voltage on any pin with respect to ground (v ss ).......................................................................................-0.5 to v cc +0.5v input current on any pin during overload condition ..................................................................................-1 0mato+10ma absolute sum of all input currents during overload condition ..................................................................| 100 ma | power dissipation............................................................................................................... ........................tbd note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the oper- ational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during overload conditions (v in > v cc or v in < v ss ) the voltage on v cc pins with respect to ground (v ss ) must not exceed the values defined by the absolute maximum ratings.
gms90c320 22 oct. 2000 ver 1.2 dc characteristics dc characteristics for gms90c320 v cc =5v+10%,-15%;v ss =0v; t a =0 cto70 c parameter symbol limit values unit test conditions min. max. input low voltage (except ea , reset) v il -0.5 0.2v cc -0.1 v- input low voltage (ea )v il1 -0.5 0.2v cc -0.3 v- input low voltage (reset) v il2 -0.5 0.2v cc +0.1 v- input high voltage (except xtal1, ea , reset) v ih 0.2v cc +0.9 v cc +0.5 v- input high voltage to xtal1 v ih1 0.7v cc v cc +0.5 v- input high voltage to ea , reset v ih2 0.6v cc v cc +0.5 v- output low voltage (ports 1, 2, 3) v ol - 0.3 0.45 1.0 v i ol =100 m a i ol =1.6ma 1) i ol =3.5ma output low voltage (port0,ale,psen ) v ol1 - 0.3 0.45 1.0 v i ol =200 m a i ol =3.2ma 1) i ol =7.0ma output high voltage (ports 1, 2, 3) v oh 2.4 0.9v cc -v i oh =-80 m a i oh =-10 m a output high voltage (port 0 in external bus mode, ale, psen ) v oh1 2.4 0.9v cc -v i oh =-800 m a 2) i oh =-80 m a 2) logic 0 input current (ports 1, 2, 3) i il -10 -50 m a v in =0.45v logical 1-to-0 transition cur- rent (ports 1, 2, 3) i tl -65 -650 m a v in =2.0v input leakage current (port 0, ea ) i li - 1 m a 0.45 < v in < v cc pin capacitance c io -10pf f c =1mhz, t a =25 c power supply current: active mode, 12mhz 3) idle mode, 12mhz 3) active mode, 24 mhz 3) idle mode, 24mhz 3) active mode, 40 mhz 3) idle mode, 40 mhz 3) active mode, 50 mhz 3) idle mode, 50 mhz 3) power down mode 3) i cc i cc i cc i cc i cc i cc i cc i cc i pd - - - - - - - - - 16 7.5 26 13.5 44 18 55 22.5 50 ma ma ma ma ma ma ma ma m a v cc =5v 4) v cc =5v 5) v cc =5v 4) v cc =5v 5) v cc =5v 4) v cc =5v 5) v cc =5v 4) v cc =5v 5) v cc =5.5v 6)
gms90c320 oct. 2000 ver 1.2 23 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and port 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. in the worst case ( capacitive loading: > 50pf at 3.3v, > 100pf at 5v), the noise pulse on ale line may exceed 0.8v. in such cases it may be desir able to qualify ale with a schmitt-trigger, or use an address latch with a schm itt- trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v cc specification when the address lines are stabilizing. 3) i cc max at other frequencies is given by: active mode: i cc =1.0 | osc +3.16 idle mode: i cc =0.37 | osc +3.63 where | osc is the oscillator frequency in mhz. i cc values are given in ma and measured at v cc =5v. 4) i cc (active mode) is measured with: xtal1 driven with t clch ,t chcl =5ns,v il =v ss +0.5v,v ih =v cc - 0.5v; xtal2 = n.c.; ea =port0=reset=v cc ; all other pins are disconnected. i cc would be slightly higher if a crystal oscillator is used (appr. 1ma). 5) i cc (idle mode) is measured with all output pins disconnected and with all peripherals disabled; xtal1 driven with t clch ,t chcl =5ns,v il =v ss +0.5v,v ih =v cc - 0.5v; xtal2 = n.c.; reset=ea =v ss ;port0=v cc ; all other pins are disconnected; 6) i pd (power down mode) is measured under following conditions: ea =port0=v cc ; reset = v ss ; xtal2 = n.c.; xtal1 = v ss ; all other pins are disconnected.
gms90c320 24 oct. 2000 ver 1.2 dc characteristics for gms90l320 v cc = 3.3v + 0.3v, -0.6v; v ss =0v; t a =0 cto70 c parameter symbol limit values unit test conditions min. max. input low voltage v il -0.5 0.8 v - input high voltage v ih 2.0 v cc +0.5 v- output low voltage (ports 1, 2, 3) v ol - 0.45 0.30 v i ol =1.6ma 1) i ol =100 m a 1) output low voltage (port0,ale,psen ) v ol1 - 0.45 0.30 v i ol =3.2ma 1) i ol =200 m a 1) output high voltage (ports 1, 2, 3) v oh 2.0 0.9v cc -v i oh =-20 m a i oh =-10 m a output high voltage (port 0 in external bus mode, ale, psen ) v oh1 2.0 0.9v cc -v i oh =-800 m a 2) i oh =-80 m a 2) logic 0 input current (ports 1, 2, 3) i il -1 -50 m a v in =0.45v logical 1-to-0 transition current (ports 1, 2, 3) i tl -25 -250 m a v in =2.0v input leakage current (port 0, ea ) i li - 1 m a 0.45 < v in < v cc pin capacitance c io -10pf f c =1mhz t a =25 c power supply current: active mode, 16 mhz 3) idle mode, 16mhz 3) active mode, 24mhz 3) idle mode, 24mhz 3) power down mode 3) i cc i cc i cc i cc i pd - - - - - 10 5.25 16 8.25 10 ma ma m a v cc =3.3v 4) v cc =3.3v 5) v cc =3.3v 4) v cc =3.3v 5) v cc =3.6v 6)
gms90c320 oct. 2000 ver 1.2 25 ac characteristics explanation of the ac symbols each timing symbol has 5 characters. the first character is always a t (stand for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a: address c: clock d: input data h: logic level high i: instruction (program memory contents) l: logic level low, or ale p: psen q: output data r: rd signal t: time v: valid w: wr signal x: no longer a valid logic level z: float for example, t avll = time from address valid to ale low t llpl = time from ale low to psen low
gms90c320 26 oct. 2000 ver 1.2 ac characteristics for 12mhz version external program memory characteristics v cc =5v: v cc =5v + 10%, - 15%; v ss =0v;t a =0 cto70 c (c l for port 0. ale and psen outputs = 100pf; c l for all other outputs = 80pf) v cc =3.3v: v cc =3.3v + 0.3v, - 0.6v; v ss =0v;t a =0 cto70 c (c l forport0.aleandpsen outputs = 50pf; c l for all other outputs = 50pf) variable clock: vcc = 5v: 1/t clcl =3.5mhzto12mhz vcc = 3.3v: 1/t clcl =1mhzto12mhz parameter symbol 12 mhz oscillator variable oscillator 1/t clcl = 3.5 to 12mhz unit min. max. min. max. ale pulse width t lhll 127 - 2t clcl -40 - ns address setup to ale t avll 43 - t clcl -40 - ns address hold after ale t llax 43 - t clcl -40 - ns ale low to valid instruction in t lliv -233 - 4t clcl -100 ns ale to psen t llpl 58 - t clcl -25 - ns psen pulse width t plph 215 - 3t clcl -35 - ns psen to valid instruction in t pliv -150 - 3t clcl -100 ns input instruction hold after psen t pxix 0- 0 - ns input instruction float after psen t pxiz 1) 1) interfacing the gms90c320 to devices with float times up to 75 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. -63 - t clcl -20 ns address valid after psen t pxav 1) 75 - t clcl -8 - ns address to valid instruction in t aviv -302 - 5t clcl -115 ns address float to psen t azpl -10 - -10 - ns
gms90c320 oct. 2000 ver 1.2 27 ac characteristics for 12mhz version external data memory characteristics advance information (12mhz) external clock drive parameter symbol 12 mhz oscillator variable oscillator 1/t clcl =3.5to12mhz unit min. max. min. max. rd pulse width t rlrh 400 - 6t clcl -100 - ns wr pulse width t wlwh 400 - 6t clcl -100 - ns address hold after ale t llax2 127 - 2t clcl -40 - ns rd to valid data in t rldv -252 -5t clcl -165 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -97 -2t clcl -70 ns ale to valid data in t lldv -517 -8t clcl -150 ns address to valid data in t avdv -585 -9t clcl -165 ns ale to wr or rd t llwl 200 300 3t clcl -50 3t clcl +50 ns address valid to wr or rd t avwl 203 - 4t clcl -130 - ns wr or rd high to ale high t whlh 43 123 t clcl -40 t clcl +40 ns data valid to wr transition t qvwx 33 - t clcl -50 - ns data setup before wr t qvwh 433 - 7t clcl -150 - ns data hold after wr t whqx 33 - t clcl -50 - ns address float after rd t rlaz -0 - 0ns parameter symbol variable oscillator (freq. = 3.5 to 12mhz) unit min. max. oscillator period (v cc =5v) oscillator period (v cc =3.3v) t clcl t clcl 83.3 83.3 285.7 1 ns high time t chcx 20 t clcl -t clcx ns low time t clcx 20 t clcl -t chcx ns rise time t clch -20ns fall time t chcl -20 ns
gms90c320 28 oct. 2000 ver 1.2 ac characteristics for 16mhz version external program memory characteristics v cc =5v: v cc =5v + 10%, - 15%; v ss =0v;t a =0 cto70 c (c l for port 0. ale and psen outputs = 100pf; c l for all other outputs = 80pf) v cc =3.3v: v cc =3.3v + 0.3v, - 0.6v; v ss =0v;t a =0 cto70 c (c l forport0.aleandpsen outputs = 50pf; c l for all other outputs = 50pf) variable clock: vcc = 5v: 1/t clcl =3.5mhzto16mhz vcc = 3.3v: 1/t clcl =1mhzto16mhz parameter symbol 16 mhz oscillator variable oscillator 1/t clcl =3.5to16mhz unit min. max. min. max. ale pulse width t lhll 85 - 2t clcl -40 - ns address setup to ale t avll 23 - t clcl -40 - ns address hold after ale t llax 43 - t clcl -40 - ns ale low to valid instruction in t lliv -150 -4t clcl -100 ns ale to psen t llpl 38 - t clcl -25 - ns psen pulse width t plph 153 - 3t clcl -35 - ns psen to valid instruction in t pliv -88 -3t clcl -100 ns input instruction hold after psen t pxix 0- 0 -ns input instruction float after psen t pxiz 1) 1) interfacing the gms90c320 to devices with float times up to 35 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. -43 - t clcl -20 ns address valid after psen t pxav 1) 55 - t clcl -8 - ns address to valid instruction in t aviv -198 -5t clcl -115 ns address float to psen t azpl -10 - -10 - ns
gms90c320 oct. 2000 ver 1.2 29 ac characteristics for 16mhz external data memory characteristics advance information (16mhz) external clock drive parameter symbol 16 mhz oscillator variable oscillator 1/t clcl =3.5to16mhz unit min. max. min. max. rd pulse width t rlrh 275 - 6t clcl -100 - ns wr pulse width t wlwh 275 - 6t clcl -100 - ns address hold after ale t llax2 127 - 2t clcl -40 - ns rd to valid data in t rldv -183 -5t clcl -130 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -75 -2t clcl -50 ns ale to valid data in t lldv -350 -8t clcl -150 ns address to valid data in t avdv -398 -9t clcl -165 ns ale to wr or rd t llwl 138 238 3t clcl - 50 3t clcl +50 ns address valid to wr or rd t avwl 120 - 4t clcl -130 - ns wr or rd high to ale high t whlh 28 97 t clcl - 35 t clcl +35 ns data valid to wr transition t qvwx 13 - t clcl - 50 - ns data setup before wr t qvwh 288 - 7t clcl -150 - ns data hold after wr t whqx 23 - t clcl - 40 - ns address float after rd t rlaz -0 - 0ns parameter symbol variable oscillator (freq. = 3.5 to 16mhz) unit min. max. oscillator period t clcl 62.5 285.7 ns high time t chcx 17 t clcl -t clcx ns low time t clcx 17 t clcl -t chcx ns rise time t clch -17ns fall time t chcl -17 ns
gms90c320 30 oct. 2000 ver 1.2 ac characteristics for 24mhz version external program memory characteristics v cc =5v: v cc =5v + 10%, - 15%; v ss =0v;t a =0 cto70 c (c l for port 0. ale and psen outputs = 100pf; c l for all other outputs = 80pf) v cc =3.3v: v cc =3.3v + 0.3v, - 0.6v; v ss =0v;t a =0 cto70 c (c l forport0.aleandpsen outputs = 50pf; c l for all other outputs = 50pf) variable clock: vcc = 5v: 1/t clcl =3.5mhzto24mhz vcc = 3.3v: 1/t clcl =1mhzto24mhz parameter symbol 24 mhz oscillator variable oscillator 1/t clcl =3.5to24mhz unit min. max. min. max. ale pulse width t lhll 43 - 2t clcl -40 - ns address setup to ale t avll 17 - t clcl -25 - ns address hold after ale t llax 17 - t clcl -25 - ns ale low to valid instruction in t lliv -80 -4t clcl -87 ns ale to psen t llpl 22 - t clcl -20 - ns psen pulse width t plph 95 - 3t clcl -30 - ns psen to valid instruction in t pliv -60 -3t clcl -65 ns input instruction hold after psen t pxix 0- 0 -ns input instruction float after psen t pxiz 1) 1) interfacing the gms90c320 to devices with float times up to 35 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. -32 - t clcl -10 ns address valid after psen t pxav 1) 37 - t clcl -5 - ns address to valid instruction in t aviv -148 - 5t clcl -60 ns address float to psen t azpl -10 - -10 - ns
gms90c320 oct. 2000 ver 1.2 31 ac characteristics for 24mhz external data memory characteristics advance information (24mhz) external clock drive parameter symbol 24 mhz oscillator variable oscillator 1/t clcl =3.5to24mhz unit min. max. min. max. rd pulse width t rlrh 180 - 6t clcl -70 - ns wr pulse width t wlwh 180 - 6t clcl -70 - ns address hold after ale t llax2 56 - 2t clcl -27 - ns rd to valid data in t rldv -118 - 5t clcl -90 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -63 -2t clcl -20 ns ale to valid data in t lldv -200 -8t clcl -133 ns address to valid data in t avdv -220 -9t clcl -155 ns ale to wr or rd t llwl 75 175 3t clcl -50 3t clcl +50 ns address valid to wr or rd t avwl 67 - 4t clcl -97 - ns wr or rd high to ale high t whlh 17 67 t clcl -25 t clcl +25 ns data valid to wr transition t qvwx 5-t clcl -37 - ns data setup before wr t qvwh 170 - 7t clcl -122 - ns data hold after wr t whqx 15 - t clcl -27 - ns address float after rd t rlaz -0 - 0ns table 11. parameter symbol variable oscillator (freq. = 3.5 to 24mhz) unit min. max. oscillator period t clcl 41.7 285.7 ns high time t chcx 12 t clcl -t clcx ns low time t clcx 12 t clcl -t chcx ns rise time t clch -12ns fall time t chcl -12 ns
gms90c320 32 oct. 2000 ver 1.2 ac characteristics for 40mhz version v cc =5v+10%, - 15%; v ss =0v;t a =0 cto70 c (c l for port 0. ale and psen outputs = 100pf; c l for all other outputs = 80pf) external program memory characteristics parameter symbol 40 mhz oscillator variable oscillator 1/t clcl =3.5to40mhz unit min. max. min. max. ale pulse width t lhll 35 - 2t clcl - 15 - ns address setup to ale t avll 10 - t clcl - 15 - ns address hold after ale t llax 10 - t clcl - 15 - ns ale low to valid instruction in t lliv -55 -4t clcl - 45 ns ale to psen t llpl 10 - t clcl - 15 - ns psen pulse width t plph 60 - 3t clcl - 15 - ns psen to valid instruction in t pliv -25 -3t clcl - 50 ns input instruction hold after psen t pxix 0- 0 -ns input instruction float after psen t pxiz 1) 1) interfacing the gms90c320 to devices with float times up to 20 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. -15 - t clcl - 10 ns address valid after psen t pxav 1) 20 - t clcl - 5-ns address to valid instruction in t aviv -65 -5t clcl - 60 ns address float to psen t azpl -5 - -5 - ns
gms90c320 oct. 2000 ver 1.2 33 ac characteristics for 40mhz external data memory characteristics advance information (40mhz) external clock drive parameter symbol at 40 mhz clock variable clock 1/t clcl =3.5to40mhz unit min. max. min. max. rd pulse width t rlrh 120 - 6t clcl -30 - ns wr pulse width t wlwh 120 - 6t clcl -30 - ns address hold after ale t llax2 10 - t clcl -15 - ns rd to valid data in t rldv -75 -5t clcl -50 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -38 -2t clcl -12 ns ale to valid data in t lldv -150 - 8t clcl -50 ns address to valid data in t avdv -150 - 9t clcl -75 ns ale to wr or rd t llwl 60 90 3t clcl -15 3t clcl +15 ns address valid to wr or rd t avwl 70 - 4t clcl -30 - ns wr or rd high to ale high t whlh 10 40 t clcl -15 t clcl +15 ns data valid to wr transition t qvwx 5-t clcl -20 - ns data setup before wr t qvwh 125 - 7t clcl -50 - ns data hold after wr t whqx 5-t clcl -20 - ns address float after rd t rlaz -0 - 0ns parameter symbol variable oscillator (freq. = 3.5 to 40mhz) unit min. max. oscillator period t clcl 25 285.7 ns high time t chcx 10 t clcl -t clcx ns low time t clcx 10 t clcl -t chcx ns rise time t clch -10ns fall time t chcl -10 ns
gms90c320 34 oct. 2000 ver 1.2 ac characteristics for 50mhz version v cc =5v+10%, - 15%; v ss =0v;t a =0 cto70 c (c l for port 0. ale and psen outputs = 100pf; c l for all other outputs = 80pf) variable clock : v cc =5v,1/ t clcl =3.5mhzto50mhz external program memory characteristics parameter symbol 50 mhz oscillator variable oscillator 1/t clcl =3.5to50mhz unit min. max. min. max. ale pulse width t lhll 25 - 2t clcl - 15 - ns address setup to ale t avll 5-t clcl - 15 - ns address hold after ale t llax 5-t clcl - 15 - ns ale low to valid instruction in t lliv -40 -4t clcl - 40 ns ale to psen t llpl 5-t clcl - 15 - ns psen pulse width t plph 45 - 3t clcl - 15 - ns psen to valid instruction in t pliv -20 -3t clcl - 40 ns input instruction hold after psen t pxix 0- 0 -ns input instruction float after psen t pxiz 1) 1) interfacing the gms90c320 to devices with float times up to 20 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. -10 - t clcl - 10 ns address valid after psen t pxav 1) 15 - t clcl - 5-ns address to valid instruction in t aviv -45 -5t clcl - 55 ns address float to psen t azpl -5 - -5 - ns
gms90c320 oct. 2000 ver 1.2 35 ac characteristics for 50mhz external data memory characteristics advance information (50mhz) external clock drive parameter symbol at 50 mhz clock variable clock 1/t clcl =3.5to50mhz unit min. max. min. max. rd pulse width t rlrh 90 - 6t clcl -30 - ns wr pulse width t wlwh 90 - 6t clcl -30 - ns address hold after ale t llax2 25 - 2t clcl -15 - ns rd to valid data in t rldv -60 -5t clcl -40 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -28 -2t clcl -12 ns ale to valid data in t lldv - 120 - 8t clcl -40 ns address to valid data in t avdv - 125 - 9t clcl -55 ns ale to wr or rd t llwl 45 75 3t clcl -15 3t clcl +15 ns address valid to wr or rd t avwl 50 - 4t clcl -30 - ns wr or rd high to ale high t whlh 535t clcl -15 t clcl +15 ns data valid to wr transition t qvwx 5-t clcl -15 - ns data setup before wr t qvwh 100 - 7t clcl -40 - ns data hold after wr t whqx 5-t clcl -15 - ns address float after rd t rlaz -0 - 0ns parameter symbol variable oscillator (freq. = 3.5 to 50mhz) unit min. max. oscillator period t clcl 20 285.7 ns high time t chcx 10 t clcl -t clcx ns low time t clcx 10 t clcl -t chcx ns rise time t clch -10ns fall time t chcl -10 ns
gms90c320 36 oct. 2000 ver 1.2 figure 4 external program memory read cycle t lhll t pxav t pxiz t pxix t llax t lliv t pliv t plph t azpl t llpl t avll a0-a7 instr. in a0-a7 a8-a15 a8-a15 t aviv ale psen port 0 port 2
gms90c320 oct. 2000 ver 1.2 37 figure 5 external data memory read cycle figure 6 external data memory write cycle t lhll p2.0-p2.7 or a8-a15 from dph a8-a15 from pch ale psen port 0 port 2 rd t llwl data in a0-a7 from pcl instr. in a0-a7 from t llax2 t avwl t avll t avdv t rlaz t lldv t rlrh t rldv t rhdx t rhdz t whlh ri or dpl t lhll p2.0-p2.7 or a8-a15 from dph a8-a15 from pch ale psen port 0 port 2 wr t llwl data out a0-a7 from pcl instr. in a0-a7 from t llax t avwl t avll t wlwh t whqx t whlh ri or dpl t qvwx t qvwh
gms90c320 38 oct. 2000 ver 1.2 figure 7 ac testing: input, output waveforms figure 8 float waveforms figure 9 external clock cycle ac inputs during testing are driven at v cc - 0.5v for a logic 1 and 0.45v for a logic 0. 0.2v cc + 0.9 0.2v cc - 0.1 test points v cc - 0.5v 0.45v timing measurements are made a v ih m in for a logic 1 and v ilm ax for a logic 0. v load + 0.1 v load - 0.1 timing reference points 0.2v cc - 0.1 v oh - 0.1 v ol + 0.1 v load for timing purposes a port pin is no longer floating when a 100mv change from load voltage i ol /i oh 3 20ma. occurs and begins to float when a 100mv change from the loaded v oh /v ol level occurs. t chcl t clch t clcx t clcl t chcx 0.2 v cc - 0.1 0.7 v cc v cc - 0.5v 0.45v
gms90c320 oct. 2000 ver 1.2 39 oscillator circuit figure 10 recommended oscillator circuits oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. xtal2 p-lcc-44/pin 20 p-dip-40/pin 18 m-qfp-44/pin 14 xtal1 p-lcc-44/pin 21 p-dip-40/pin 19 m-qfp-44/pin 15 crystal oscillator mode driving from external source xtal2 p-lcc-44/pin 20 p-dip-40/pin 18 m-qfp-44/pin 14 xtal1 p-lcc-44/pin 21 p-dip-40/pin 19 m-qfp-44/pin 15 external oscillator signal n.c. c2 c1 c1, c2 = 30pf 10pf for crystals for ceramic resonators, contact resonator manufacturer.
gms90c320 40 oct. 2000 ver 1.2 plastic package p-lcc-44 (plastic leaded chip-carrier) 0.180 0.165 unit: inch 44plcc 0.012 0.0075 0.120 0.090 0.032 0.026 0.630 0.590 min. 0.020 0.656 0.650 0.695 0.685 0.656 0.650 0.695 0.685 0.050 bsc 0.021 0.013
gms90c320 oct. 2000 ver 1.2 41 plastic package p-dip-40 (plastic dual in-line package) unit: inch 2.075 2.045 0.200 max. 0.022 0.015 0.065 0.045 0.100 bsc 0.550 0.530 0.600 bsc 0-15 0 . 0 1 2 0 . 0 0 8 40dip 0.140 0.120 min. 0.015
gms90c320 42 oct. 2000 ver 1.2 plastic package p-mqfp-44 (plastic metric quad flat package) 2.35 max. see detail a 1.03 0.73 0-7 0.25 0.10 1.60 ref detail a unit: mm 0.45 0.30 0.80 bsc 2.10 1.95 p-mqfp-44 0 . 1 3 0 . 2 3 10.10 9.90 13.45 12.95 10.10 9.90 13.45 12.95

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